1. Field of the Invention
The present invention relates to a low-inductance circuit arrangement for power semiconductor modules. More specifically, the present invention relates to a low-inductance circuit arrangement for high-speed modem power semiconductor modules having low parasitic inductances and low ohmic resistance.
2. Description of the Related Art
Power transistors such as IGBTs (Insulating-Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) are conventionally known. In use, power transistors such as IGBTs and MOSFETs are regulated, i.e., switched into a conductive or non-conductive state, by applying a certain voltage between the gate and the emitter.
It is conventionally known that individual switches and power semiconductor modules may have individual constructive means to reduce parasitic inductances, certain designs are shown in, for example, EP 0 277 546, DE 39 37 045 or DE 100 37 533.
EP 0 277 546 describes a method for reducing parasitic inductances in the DC input leads of an individual switch. Here, the two DC input leads are arranged in close proximity and at least partially parallel to each other. This results in a small current-circumfused (current surrounded) surface in the area of the closely adjacent input lead arrangement and thus a lower inductance of this input lead sector. Here, the DC input leads are connected to the substrate in a positive bond by means of soldering. Similarly, DE 196 18 978 A1 discloses a comparable arrangement for the load ports, unfortunately, the entire arrangement including the substrate is not of sufficiently low inductance, since the current-circumfused (current surrounded) surfaces (see description in DE 100 37 533 C1) are too large.
DE 39 37 045 describes a method of reducing parasitic inductances in the DC input leads of a half-bridge. As shown, the two DC input leads are arranged contiguously, but with the AC input lead between the plus and minus lead, and at least partially parallel to each other. This arrangement also has the effect of reducing the size of the current-circumfused surface in the area if the adjacent arrangement of input leads and thus a relatively low inductance of this input lead sector. Here, the DC and AC leads are also connected to the substrate in a positive bond by means of soldering.
DE 100 37 533 describes a circuit arrangement with very low parasitic inductances. The description arranges the individual power transistors of the two power switches in series and in an attempt to provide finger-like contact elements between the individual power transistors. Unfortunately, the low parasitic inductances in this circuit arrangements, achieved with this pressure-contacted arrangement, are still limited.
DE 197 52 408 A1 discloses contiguously arranged port conductors some of which are attached to or arranged in a frame-like housing. Unfortunately, these port conductors are auxiliary port conductors which, in contrast to the load port conductors consisting of DC and AC port conductors, have no effect on the parasitic inductances of the power semiconductor module.
Compact power semiconductor modules are conventionally described in DE 197 19 703. This type of power semiconductor module consists of ceramic substrates with applied ribbon (or web or track-type) connectors on which semiconductor components are arranged. These semiconductor components are connected by soldering to the ribbon connectors, and they have bonded connections with other semiconductor components. The port elements on the housing wall are provided with partial surfaces from where wire bond connections are established with individual ribbon connectors of the substrate.
Unfortunately, in EP 0 277 546, while the transistors forming the individual switch are in close proximity to each other, the current can nevertheless flow through the circuit arrangement along dissimilar paths, in particular along paths of dissimilar length. This design results in dissimilar current-circumfused surfaces, dissimilar inductances for the different conduction paths, and also dissimilar ohmic resistance values for these conduction paths. As a particular detriment to this design, the design of a half-bridge with such individual switches can never be of low inductance due to the external circuitry necessary for that purpose. Consequently, considering all characteristics together, this design leads to a certain reduction in parasitic inductances of the overall system of intermediate circuit and DC/AC converter. Unfortunately, the design shown does not meet all the requirements for minimizing parasitic inductances. Neither can an arrangement of individual switches, each with its own housing, meet the requirements of a compact and/or cost-effective design of the overall system.
Similarly to the above discussion, DE 39 37 045 misses the goal of low parasitic inductance for two main reasons. First, the DC port conductors are not arranged at a minimal distance from each other, since the AC port conductor is arranged between the two DC port conductors. Consequently, the current-circumfused surface in the area of the DC port conductors is not minimal, and thus the inductances for this area are not minimal either. Secondly, the power transistors of the first and second power switches are relative far apart, which also increases the parasitic inductances. In this arrangement, the relatively large surfaces parallel to the substrate below the port conductors for the plus and AC port are contrary to the goal of compact assemblies.
In sum, the unfortunate consequence of the above-mentioned related art teachings are circuit designs having ineffective low-inductance design and result in substantially larger parasitic inductances than necessary.